Rectangular capacitors for dynamic random access memory (dram) and dual-pass lithography methods to form the same

ABSTRACT

A rectangular capacitor for dynamic random access memory (DRAM) and a dual-pass lithography method to form the same are described. For example, a capacitor includes a trench disposed in a first dielectric layer disposed above a substrate. A cup-shaped metal plate is disposed along the bottom and sidewalls of the trench. A second dielectric layer is disposed on and conformal with the cup-shaped metal plate. A trench-fill metal plate is disposed on the second dielectric layer. The second dielectric layer isolates the trench-fill metal plate from the cup-shaped metal plate. The capacitor has a rectangular or near-rectangular shape from a top-down perspective.

TECHNICAL FIELD

Embodiments of the invention are in the field of dynamic random accessmemory and, in particular, rectangular capacitors for dynamic randomaccess memory (DRAM) and dual-pass lithography methods to form the same.

BACKGROUND

For the past several decades, the scaling of features in integratedcircuits has been a driving force behind an ever-growing semiconductorindustry. Scaling to smaller and smaller features enables increaseddensities of functional units on the limited real estate ofsemiconductor chips. For example, shrinking transistor size allows forthe incorporation of an increased number of memory devices on a chip,lending to the fabrication of products with increased capacity. Thedrive for ever-more capacity, however, is not without issue. Thenecessity to optimize the performance of each device becomesincreasingly significant.

In semiconductor devices such as DRAMs (Dynamic Random Access Memory),each cell is composed of one transistor and one capacitor. In DRAMs,cells require periodic reading and refreshing. Owing to the advantagesof low price-per-unit-bit, high integration, and ability tosimultaneously perform read and write operations, DRAMs have enjoyedwidespread use in commercial applications. In the meantime, a phenomenonreferred to as “soft error” can be caused in DRAM devices by a loss ofcharge that was stored in a capacitor due to external factors, therebycausing malfunction of DRAMs. In order to prevent the occurrence of softerror, a method of enhancing the capacitance of a capacitor has beensuggested. The capacitance of the capacitor can be enhanced byincreasing the surface area of a lower electrode. Although many studieshave been investigated in the area of increasing the lower electrodesurface area, challenges are presented in formulating practicalmanufacturing processes due to the ever increasing high level ofintegration of semiconductor devices.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a comparison, from a top-down perspective, of acapacitor formed from a dual-pass lithography approach versus acapacitor formed from a single-pass lithography approach, in accordancewith an embodiment of the present invention.

FIG. 2A illustrates a cross-sectional view of a conventional capacitor.

FIG. 2B illustrates a top-down view of a conventional capacitor.

FIG. 3A illustrates a cross-sectional view of a capacitor, in accordancewith an embodiment of the present invention.

FIG. 3B illustrates a top-down view of a capacitor, in accordance withan embodiment of the present invention.

FIG. 3C illustrates a top-down view of another capacitor, in accordancewith an embodiment of the present invention.

FIG. 4A illustrates a top-down view of a conventional array ofcapacitors.

FIG. 4B illustrates a top-down view of an array of rectangular ornear-rectangular capacitors, in accordance with an embodiment of thepresent invention.

FIG. 5 is a Flowchart representing operations in a method of forming anembedded metal-insulator-metal (MIM) capacitor in accordance with anembodiment of the present invention.

DETAILED DESCRIPTION

Rectangular capacitors for dynamic random access memory (DRAM) anddual-pass lithography methods to form the same are described. In thefollowing description, numerous specific details are set forth, such aslayouts for capacitor arrays and material regimes, in order to provide athorough understanding of embodiments of the present invention. It willbe apparent to one skilled in the art that embodiments of the presentinvention may be practiced without these specific details. In otherinstances, well-known features, such as integrated circuit designlayouts, are not described in detail in order to not unnecessarilyobscure embodiments of the present invention. Furthermore, it is to beunderstood that the various embodiments shown in the Figures areillustrative representations and are not necessarily drawn to scale.

Single-pass lithography techniques involve a single exposure of aphoto-resist layer and subsequent development to provide a patternedmask for use in, e.g., patterning layers used in the fabrication ofsemiconductor devices. Square or rectangular features often end upresulting in circular or oval mask features in single-pass lithography.While circular or oval mask features may be suitable for certainapplications, others may require square or rectangular features foroptimal performance.

In accordance with embodiments of the present invention, a dual passlithography, or resist freeze, technique is used to form square orrectangular (herein referred to as “rectangular”) features ornear-square or near-rectangular (herein referred to as“near-rectangular”) features. In particular, a dual-pass lithographyapproach may be used to provide capacitors for dynamic random accessmemory (DRAM) circuits. The approach may allow for increased criticaldimension (CD) control, enabling tighter packing within an array ofcapacitors. The approach may also allow for increased capacitancesurface area, providing more effective performance for a DRAM circuit.

FIG. 1 illustrates a comparison, from a top-down perspective, of acapacitor formed from a dual-pass lithography approach versus acapacitor formed from a single-pass lithography approach, in accordancewith an embodiment of the present invention. A top-down view of acapacitor 100 formed from a dual-pass lithography approach is depictedto have an idealized rectangular geometry. On the other hand, acapacitor 102 formed from a single-pass lithography approach has an ovalgeometry.

The capacitance of the portion of the capacitor 100 shown in plane ofFIG. 1 is 2A*2B=4AB. By contrast, capacitance of the portion of thecapacitor 102 shown in plane of FIG. 1 is π*A*B. Accordingly, thecapacitance of the portion of the capacitor 100 shown in plane of FIG. 1is 1.27 times greater than the capacitance of the portion of thecapacitor 102 shown in plane of FIG. 1. Additionally, the capacitance ofthe sidewall area (formed into the plane of FIG. 1 may be increased byusing dual-pass lithography. For example, the perimeter of the capacitor100 is 2A+2B, while the perimeter of the capacitor 102 is 2*π*Sqrt((A²+B²)/2). In a specific example, such a perimeter difference leads toapproximately 16% more capacitance for the sidewalls of capacitor 100 ascompared with capacitor 102. Overall, even accounting fornon-idealities, the overall capacitance gain for a capacitor formed froma dual-pass lithography approach may be approximately in the range of10-15% as compared with a capacitor formed from a single-passlithography approach.

Disclosed herein are embedded metal-insulator-metal (MIM) capacitors forsemiconductor devices. In one embodiment, a trench is disposed in afirst dielectric layer disposed above a substrate. A cup-shaped metalplate is disposed along the bottom and sidewalls of the trench. A seconddielectric layer is disposed on and conformal with the cup-shaped metalplate. A trench-fill metal plate is disposed on the second dielectriclayer. The second dielectric layer isolates the trench-fill metal platefrom the cup-shaped metal plate. The capacitor has a rectangular ornear-rectangular shape from a top-down perspective.

Also disclosed herein are methods of fabricating embeddedmetal-insulator-metal (MIM) capacitors for semiconductor devices. In oneembodiment, a method includes forming a first patterned photo-resistlayer above a first dielectric layer above a substrate. The firstpatterned photo-resist layer includes a first pattern of lines along afirst direction. The first patterned photo-resist layer is thenhardened. Subsequently, a second patterned photo-resist layer is formedabove the first patterned photo-resist layer. The second patternedphoto-resist layer includes a second pattern of lines along a seconddirection different from the first direction. A trench is formed in thefirst dielectric layer using both the first patterned photo-resist layerand the second patterned photo-resist layer as a mask. A capacitor isthen formed in the trench.

FIG. 2 illustrates (A) a cross-sectional view and (B) a top-down view ofa conventional capacitor. Referring to FIG. 2A, a first interlayerinsulating layer 203 is formed on a semiconductor substrate 201 having acell array region 202. The first interlayer insulating layer 203 ispatterned to form contact holes exposing the semiconductor substrate 201on the cell array region 202 and the contact holes are filled with aconductive material to form a lower electrode contact plug 205 a. Anetch stop layer 207 and a second interlayer insulating layer 209 aresequentially formed on the resulting structure.

The second interlayer insulating layer 209 and the etch stop layer 207are sequentially etched in the cell array region 202 to form the lowerelectrode contact plug 5 a and a storage node hole 211 exposing thefirst interlayer insulating layer 203 around the lower electrode contactplug. After a lower electrode layer 213 is conformally stacked on theresulting structure, a planarization process is carried out to form alower electrode 213 covering a bottom and an inner sidewall of thestorage node hole 211. A dielectric layer 215 and an upper electrodelayer 217 are sequentially stacked and patterned on the semiconductorsubstrate 201.

In the conventional architecture shown in FIG. 2A, methods are availablefor increasing the height of the lower electrode as a method forincreasing the surface area of the lower electrode to increasecapacitance. In one such method, the thickness of the second interlayerinsulating layer where the lower electrode is positioned is increased.However, if the thickness of the second interlayer insulating layer isincreased, the process burden is also increased because large amount ofetching is required when the metal contact hole is formed. Thus, thereliability of the semiconductor device can be degraded. Furthermore,referring to FIG. 2B, the capacitor is conventionally formed in asingle-pass lithography approach. Such an approach may lead to circularor oval top-down perimeters, as described above.

In an aspect of the present invention, an embedded metal-insulator-metal(MIM) capacitor with a rectangular or near-rectangular perimeter isprovided. FIG. 3 illustrates (A) a cross-sectional view, (B) a firsttop-down view, and (C) a second top-down view of a capacitor, inaccordance with an embodiment of the present invention.

Referring to FIG. 3A, an embedded metal-insulator-metal (MIM) capacitor300 or 300′ for a semiconductor device includes a trench 302 disposed ina first dielectric layer 304 disposed above a substrate 306. Acup-shaped metal plate 308 is disposed along the bottom and sidewalls ofthe trench 302. A second dielectric layer 310 is disposed on andconformal with the cup-shaped metal plate 308. A trench-fill metal plate312 is disposed on the second dielectric layer 310. The seconddielectric layer 310 isolates the trench-fill metal plate 312 from thecup-shaped metal plate 308.

Referring to FIG. 3B, the capacitor 300 has a rectangular ornear-rectangular shape from a top-down perspective, with an ideallyrectangular perimeter depicted in FIG. 3B. Referring to FIG. 3C, inaccordance with an embodiment of the present invention, the capacitor300′ has a near-rectangular shape with slightly rounded corners 320. Inan embodiment, referring again to FIG. 3A, the sidewalls 322 of thetrench 302 have a vertical or near-vertical profile.

Referring again to FIG. 3A, in an embodiment, the cup-shaped metal plate308 is electrically coupled to an underlying transistor 330 disposedabove the substrate 306. In one embodiment, the transistor 330 isincluded in a dynamic random access memory (DRAM circuit). In a specificembodiment, the cup-shaped metal plate 308 is electrically coupled tothe underlying transistor 330 by a floor metal layer 326, such as acopper layer, disposed below the first dielectric layer 304.

In an embodiment, the cup-shaped metal plate 308 is composed of a copperlayer proximate to the bottom of the trench 302 and distal from thesecond dielectric layer 310, and is further composed of a metal nitridelayer proximate to the second dielectric layer 310 and distal from thebottom of the trench 302. In an embodiment, the trench-fill metal plate312 is composed of copper. In one embodiment, the metal nitride layer isa tantalum nitride layer or a titanium nitride layer. In an embodiment,one or more of the copper layer or the metal nitride layer of thecup-shaped metal plate 308 or the copper of the trench-fill metal plate312 is formed by a technique such as, but not limited to, anelectro-chemical deposition process, an electro-less deposition process,a chemical vapor deposition process, an atomic layer deposition (ALD)process, or a reflow process. It is to be understood that silver,aluminum, or an alloy of copper, silver or aluminum may be used in placeof the above described copper. Also, the cup-shaped metal plate 308 maybe a single layer feature formed from copper, silver, aluminum, or analloy thereof. In an alternative embodiment, trench-fill metal plate 312includes a multiple layer structure.

In an embodiment, the first dielectric layer 304 is a low-K dielectriclayer (a layer with a dielectric constant less than 4 for silicondioxide). In one embodiment, the first dielectric layer 304 is formed bya process such as, but not limited to, a spin-on process, a chemicalvapor deposition process, or a polymer-based chemical vapor depositionprocess. In a specific embodiment, the first dielectric layer 304 isformed by a chemical vapor deposition process involving silane or anorgano-silane as a precursor gas. In an embodiment, the first dielectriclayer 304 is composed of a material that does not significantlycontribute to leakage current between a series of metal interconnectssubsequently formed in or on the first dielectric layer 304. In oneembodiment, the first dielectric layer 304 is composed of a material inthe range of 2.5 to less than 4. In a particular embodiment, the firstdielectric layer 304 is composed of a material such as, but not limitedto, a silicate or a carbon-doped oxide with 0-10% porosity. In anotherembodiment, however, the first dielectric layer 304 is composed ofsilicon dioxide.

In an embodiment, the second dielectric layer 310 is composed a high-Kdielectric layer (a layer with a dielectric constant greater than 4 forsilicon dioxide). In one embodiment, the second dielectric layer 310 isformed by an atomic vapor deposition process or a chemical vapordeposition process and is composed of a material such as, but notlimited to, silicon oxy-nitride, hafnium oxide, zirconium oxide, hafniumsilicate, hafnium oxy-nitride or lanthanum oxide. In another embodiment,however, the second dielectric layer 310 is composed of silicon dioxide.

In an embodiment, substrate 306 is composed of a material suitable forsemiconductor device fabrication. In one embodiment, substrate 306 is abulk substrate composed of a single crystal of a material which mayinclude, but is not limited to, silicon, germanium, silicon-germanium ora III-V compound semiconductor material. In another embodiment,substrate 306 includes a bulk layer with a top epitaxial layer. In aspecific embodiment, the bulk layer is composed of a single crystal of amaterial which may include, but is not limited to, silicon, germanium,silicon-germanium, a III-V compound semiconductor material or quartz,while the top epitaxial layer is composed of a single crystal layerwhich may include, but is not limited to, silicon, germanium,silicon-germanium or a III-V compound semiconductor material. In anotherembodiment, substrate 306 includes a top epitaxial layer on a middleinsulator layer which is above a lower bulk layer. The top epitaxiallayer is composed of a single crystal layer which may include, but isnot limited to, silicon (e.g., to form a silicon-on-insulator (SOI)semiconductor substrate), germanium, silicon-germanium or a III-Vcompound semiconductor material. The insulator layer is composed of amaterial which may include, but is not limited to, silicon dioxide,silicon nitride or silicon oxy-nitride. The lower bulk layer is composedof a single crystal which may include, but is not limited to, silicon,germanium, silicon-germanium, a III-V compound semiconductor material orquartz. Substrate 306 may further include dopant impurity atoms.

In accordance with an embodiment of the present invention, substrate 306has thereon an array of complimentary metal-oxide-semiconductor (CMOS)transistors fabricated in a silicon substrate and encased in adielectric layer. A plurality of metal interconnects may be formed abovethe transistors, and on the surrounding dielectric layer, and are usedto electrically connect the transistors to form an integrated circuit.In one embodiment, the integrated circuit is used for a DRAM.

Although only a single capacitor was described in association with FIG.3, an array of capacitors may be included in a single product. Byforming capacitors with rectangular or near-rectangular perimeters, froma top-down perspective, increased critical dimension (CD) control may beachieved, enabling tighter packing within the array of capacitors. Forexample, in accordance with an embodiment of the present invention,electrical results show that with similar spacing the rectangular shapeprovides an extra 12% capacitance over the oval shape. Additionally,resulting from the improved CD control, capacitor-to-capacitor spacingcan be reduced. Such a reduction in spacing, i.e. increase in packingdensity, may provide up to, or even more than, a 30% capacitanceincrease with dual-pass lithography versus single-pass lithography.

Thus, in an aspect of the present invention, an array of embeddedmetal-insulator-metal (MIM) capacitors with rectangular ornear-rectangular perimeters is provided. FIG. 4 illustrates a top-downview of (A) a conventional array of capacitors, and (B) an array ofrectangular or near-rectangular capacitors, in accordance with anembodiment of the present invention.

Referring to FIG. 4A, a conventional array of capacitors 400A has anarray of oval perimeters 402A from a top-down perspective. Such an arraymay be formed by a single-pass lithography approach. By contrast,referring to FIG. 4B, in an aspect of the present invention, an array ofcapacitors 400B has an array of rectangular or near-rectangularperimeters 402B from a top-down perspective. Such an array may be formedby a dual-pass lithography approach.

Referring again to FIG. 4B, an array 400B of embeddedmetal-insulator-metal (MIM) capacitors for, e.g., an array ofsemiconductor devices is depicted. The capacitors include a plurality oftrenches disposed in a first dielectric layer disposed above asubstrate. A plurality of cup-shaped metal plates is included, eachdisposed along the bottom and sidewalls of a corresponding trench. Aplurality of second dielectric layers is also included, each disposed onand conformal with a corresponding cup-shaped metal plate. A pluralityof trench-fill metal plates is also included, each disposed on acorresponding second dielectric layer, the second dielectric layerisolating the corresponding trench-fill metal plate from thecorresponding cup-shaped metal plate. The array of capacitors forms agrid pattern as depicted in FIG. 4B. Furthermore, each of the capacitorshas a rectangular or near-rectangular shape from a top-down perspective,as depicted in FIGS. 3B and 4B. In one embodiment, from the top-downperspective, each capacitor has the near-rectangular shape with slightlyrounded corners, as depicted in and described in association with FIG.3C.

In an embodiment, the sidewalls of each trench have a vertical ornear-vertical profile. In an embodiment, each cup-shaped metal plate iselectrically coupled to an underlying transistor disposed above thesubstrate. In one embodiment, the transistor is included in a dynamicrandom access memory (DRAM circuit). In a specific embodiment, eachcup-shaped metal plate is electrically coupled to the underlyingtransistor by a floor metal layer disposed below the first dielectriclayer. In an embodiment, each cup-shaped metal plate is composed of acopper layer proximate to the bottom of the corresponding trench anddistal from the corresponding second dielectric layer, and is alsocomposed of a metal nitride layer proximate to the corresponding seconddielectric layer and distal from the bottom of the corresponding trench.In an embodiment, each trench-fill metal plate is composed of copper. Inan embodiment, the first dielectric layer is a low-K dielectric layer.In an embodiment, each second dielectric layer is a high-K dielectriclayer.

In another aspect of the present invention, a method of fabricating anembedded metal-insulator-metal (MIM) capacitor for semiconductor devicesis provided. FIG. 5 is a Flowchart 500 representing operations in amethod of forming an embedded metal-insulator-metal (MIM) capacitor inaccordance with an embodiment of the present invention.

Referring to operation 502 of Flowchart 500, a first patternedphoto-resist layer is formed above a first dielectric layer above asubstrate. The first patterned photo-resist layer has a first pattern oflines along a first direction. A photo-resist layer used to form thefirst patterned photo-resist layer may be composed of a materialsuitable for use in a lithographic process. In one embodiment, thephoto-resist layer is formed by first masking a blanket layer ofphoto-resist material. The blanket layer of photo-resist material isthen exposed to a light source and subsequently developed, e.g., bytreating with a wet chemical solution, to provide the first patternedphoto-resist layer.

In an embodiment, the portions of the photo-resist layer exposed to thelight source are removed upon developing the photo-resist layer. Thus,in an embodiment, the photo-resist layer is composed of a positivephoto-resist material. In a specific embodiment, the photo-resist layeris composed of a positive photo-resist material such as, but not limitedto, a 248 nm resist, a 193 nm resist, a 157 nm resist or a phenolicresin matrix with a diazonaphthoquinone sensitizer. In anotherembodiment, the portions of the photo-resist layer exposed to the lightsource are retained upon developing the photo-resist layer. Thus, inanother embodiment, the photo-resist layer is composed of a negativephoto-resist material. In a specific embodiment, the photo-resist layeris composed of a negative photo-resist material such as, but not limitedto, poly-cis-isoprene or poly-vinyl-cinnamate.

Referring to operation 504 of Flowchart 500, the first patternedphoto-resist layer is hardened. In accordance with an embodiment of thepresent invention, the first patterned photo-resist layer is hardened toa degree suitable to withstand formation of a second patternedphoto-resist layer on or above the first patterned photo-resist layer.In one embodiment, the first patterned photo-resist layer is hardenedthrough a technique such as, but not limited to, a curing process or afreezing process.

Referring to operation 506 of Flowchart 500, subsequent to hardening thefirst patterned photo-resist layer, a second patterned photo-resistlayer is formed above the first patterned photo-resist layer. The secondpatterned photo-resist layer has a second pattern of lines along asecond direction different from the first direction. In accordance withan embodiment of the present invention, the first direction isorthogonal to the second direction. The second patterned photo-resistlayer may be formed in the same or similar manner and from the same orsimilar material as the first patterned photo-resist layer, describedabove.

Referring to operation 508 of Flowchart 500, a trench is formed in thefirst dielectric layer using both the first patterned photo-resist layerand the second patterned photo-resist layer as a mask. In accordancewith an embodiment of the present invention, the sidewalls of the trenchhave a vertical or near-vertical profile.

Referring to operation 510 of Flowchart 500, a capacitor is formed inthe trench. In accordance with an embodiment of the present invention,the capacitor has a rectangular or near-rectangular shape from atop-down perspective. In one embodiment, from the top-down perspective,the capacitor has the near-rectangular shape with slightly roundedcorners.

In an embodiment, forming the capacitor includes forming a cup-shapedmetal plate along the bottom and sidewalls of the trench, forming asecond dielectric layer on and conformal with the cup-shaped metalplate, and forming a trench-fill metal plate on the second dielectriclayer, the second dielectric layer isolating the trench-fill metal platefrom the cup-shaped metal plate. In one embodiment, the cup-shaped metalplate is composed of a copper layer proximate to the bottom of thetrench and distal from the second dielectric layer, and is furthercomposed of a metal nitride layer proximate to the second dielectriclayer and distal from the bottom of the trench. The trench-fill metalplate is composed of copper. In one embodiment, the first dielectriclayer is a low-K dielectric layer, and the second dielectric layer is ahigh-K dielectric layer.

In an embodiment, the method of forming an embeddedmetal-insulator-metal (MIM) capacitor further includes electricallycoupling the capacitor to an underlying transistor disposed above thesubstrate. In one embodiment, the transistor is included in a dynamicrandom access memory (DRAM circuit). In one embodiment, the cup-shapedmetal plate is electrically coupled to the underlying transistor by afloor metal layer disposed below the first dielectric layer.

Thus, rectangular capacitors for dynamic random access memory (DRAM) anddual-pass lithography methods to form the same have been disclosed. Inan embodiment, a capacitor includes a trench disposed in a firstdielectric layer disposed above a substrate. A cup-shaped metal plate isdisposed along the bottom and sidewalls of the trench. A seconddielectric layer is disposed on and conformal with the cup-shaped metalplate. A trench-fill metal plate is disposed on the second dielectriclayer. The second dielectric layer isolates the trench-fill metal platefrom the cup-shaped metal plate. The capacitor has a rectangular ornear-rectangular shape from a top-down perspective. In one embodiment,from the top-down perspective, the capacitor has the near-rectangularshape with slightly rounded corners. In one embodiment, the sidewalls ofthe trench have a vertical or near-vertical profile. In one embodiment,the cup-shaped metal plate is electrically coupled to an underlyingtransistor disposed above the substrate, and the transistor included ina dynamic random access memory (DRAM) circuit.

1. An embedded metal-insulator-metal (MIM) capacitor for a semiconductordevice, the capacitor comprising: a trench disposed in a firstdielectric layer disposed above a substrate; a cup-shaped metal platedisposed along the bottom and sidewalls of the trench; a seconddielectric layer disposed on and conformal with the cup-shaped metalplate; and a trench-fill metal plate disposed on the second dielectriclayer, the second dielectric layer isolating the trench-fill metal platefrom the cup-shaped metal plate, wherein the capacitor has a rectangularor near-rectangular shape from a top-down perspective.
 2. The capacitorof claim 1, wherein, from the top-down perspective, the capacitor hasthe near-rectangular shape with slightly rounded corners.
 3. Thecapacitor of claim 1, wherein the sidewalls of the trench comprise avertical or near-vertical profile.
 4. The capacitor of claim 1, whereinthe cup-shaped metal plate is electrically coupled to an underlyingtransistor disposed above the substrate, the transistor included in adynamic random access memory (DRAM) circuit.
 5. The capacitor of claim4, wherein the cup-shaped metal plate is electrically coupled to theunderlying transistor by a floor metal layer disposed below the firstdielectric layer.
 6. The capacitor of claim 1, wherein the cup-shapedmetal plate comprises a copper layer proximate to the bottom of thetrench and distal from the second dielectric layer, and comprises ametal nitride layer proximate to the second dielectric layer and distalfrom the bottom of the trench, and wherein the trench-fill metal platecomprises copper.
 7. The capacitor of claim 1, wherein the firstdielectric layer is a low-K dielectric layer, and the second dielectriclayer is a high-K dielectric layer. 8.-13. (canceled)
 14. An array ofembedded metal-insulator-metal (MIM) capacitors for an array ofsemiconductor devices, the capacitors comprising: a plurality oftrenches disposed in a first dielectric layer disposed above asubstrate; a plurality of cup-shaped metal plates, each disposed alongthe bottom and sidewalls of a corresponding trench; a plurality ofsecond dielectric layers, each disposed on and conformal with acorresponding cup-shaped metal plate; and a plurality of trench-fillmetal plates, each disposed on a corresponding second dielectric layer,the second dielectric layer isolating the corresponding trench-fillmetal plate from the corresponding cup-shaped metal plate, wherein thearray of capacitors forms a grid pattern, and wherein each of thecapacitors has a rectangular or near-rectangular shape from a top-downperspective.
 15. The array of capacitors of claim 14, wherein, from thetop-down perspective, each capacitor has the near-rectangular shape withslightly rounded corners.
 16. The array of capacitors of claim 14,wherein the sidewalls of each trench comprise a vertical ornear-vertical profile.
 17. The array of capacitors of claim 14, whereineach cup-shaped metal plate is electrically coupled to an underlyingtransistor disposed above the substrate, the transistor included in adynamic random access memory (DRAM circuit).
 18. The array of capacitorsof claim 17, wherein each cup-shaped metal plate is electrically coupledto the underlying transistor by a floor metal layer disposed below thefirst dielectric layer.
 19. The array of capacitors of claim 14, whereineach cup-shaped metal plate comprises a copper layer proximate to thebottom of the corresponding trench and distal from the correspondingsecond dielectric layer, and comprises a metal nitride layer proximateto the corresponding second dielectric layer and distal from the bottomof the corresponding trench, and wherein each trench-fill metal platecomprises copper.
 20. The array of capacitors of claim 14, wherein thefirst dielectric layer is a low-K dielectric layer, and each seconddielectric layer is a high-K dielectric layer.